1. Field of the Invention
The present invention relates to an ATM (asynchronous transfer mode) system for interleaving 8 bit parallel cell and a method thereof, in which ATM cells may be interleaved by parallel 8 bits in such a way that 40 bits in a cell header are positioned over the whole cell including the header and a payload thereof with an interval of 10 bits, when the cells are being transferred through wireless channels, so that cell loss rate due to burst error characteristics is reduced.
2. Description of the Conventional Art
Conventionally, asynchronous transfer mode cells are transferred in optical fiber or wireline environments and protocols thereof are fitted to corresponding situations.
Referring to algorithm for abolishing cells, error of 1 bit in an ATM cell header may be corrected, but a cell should be abolished if 2 or more bit errors occur.
If the conventional cell abolish algorithm is adopted in cell transfer by using wireless channels and environments thereof are kept equally to that of the conventional in wire environments, then a random BER (Burst Error Rate) as well as a continuous BER are occur simultaneously due to the wireless channel characteristics, thereby increasing a cell loss rate and degrading the transfer performance.
Conventionally, a serial interleaver interleaves all data by bit while writing the data in the memory.
However, the conventional serial interleaver has a disadvantage that the serial interleaver can not perform direct interleaving, when the interleaver is provided to a parallel circuit for processing conventional ATM cells or a device, so that an additional serial/parallel converter is required.
The conventional serial interleaver has another disadvantage that the stability or operation speed of the whole circuitry is limitative, since the circuitry requires 8 times higher clocks than the conventional circuitry. Especially, the conventional serial interleaver has a further disadvantage that a random BER as well as a continuous BER occur simultaneously due to characteristics of the wireless channel, so that a cell loss rate increases and the transfer performance is degraded.
The present invention is derived to resolve the disadvantages of the conventional techniques and it is an object of the present invention to provide an ATM system for interleaving cells by parallel 8 bits and a method thereof, in which all ATM cells are processed by parallel 8 bits in all interleaving process, so that an 8 bit interleaver is directly added to the conventional ATM system and performs cell interleaving in parallel without any serial/parallel converting circuit, thereby achieving a device which, is proper for wireless environments of low speed.
According to one aspect of the present invention, the above objects may be resolved by an interleaver for interleaving cells by parallel 8 bits, which includes:
an ATM cell header buffer for storing an ATM cell header into a predetermined cell header buffer according to a control signal output from a write controller, or outputting data by 1 bit at a predetermined buffer according to a control signal output from a read controller,
a write controller for controlling to separately store a cell header and a payload according to a start signal representative of a beginning of cell input and an interleaver signal,
a read controller for controlling to sequentially output data which are mixed with the header and the payload in an interleaver memory,
an interleaver memory for writing a data of a ATM cell payload to a predetermined buffer among 9 buffers according to a control signal output from the write controller, and
a multiplexor for multiplexing 12 byte data output from the interleaver memory according to a controller signal from the read controller.
According to the ATM system for interleaving cells by parallel 8 bits of the present invention, the interleaver memory includes a decoder for selecting a buffer to write data among nine byte unit buffers and a converter for converting 9 bytes input from the decoder to 10 bytes.
According to the ATM system having an interleaver of 8 bit parallel cell units of the present invention, the converter comprises a plurality of D flip-flops in which the 9 bytes are stored, and a mixer for mixing the 9 byte data of the D flip-flop with 1 byte of the header to make 10 bytes.
According to one aspect of the present invention, the above objects may be resolved by a method for interleaving ATM cells by parallel 8 bits, which includes the steps of:
inputting ATM cell data to an interleaver from an HEC processing part of an ATM physical layer in an ATM network;
delaying the input data for 1 clock period by a D flip-flop of the interleaver for assuring an operation time of a controller;
generating an enabling signal to an ATM cell header buffer according to a start signal representative of cell input from the write controller and a signal representative of interleaving method;
generating an enabling signal for writing data and an address signal representative of position to write the data;
generating start byte of the enabling signal and the start signal to the read controller;
transmitting from the read controller to the ATM cell header buffer, a header 1 bit output enabling signal after two clocks of the start signal and a control signal to output a header bit of a next byte after outputting 8 bits and shifting header buffers of 5 bytes;
storing ATM cell headers at corresponding positions according to the control signal output from the write controller and outputting data by 1 bit at a predetermined buffer according to a control signal output from the read controller;
writing payload data of the ATM cell at a predetermined position in an interleaver memory while outputting data of 12 bytes which are mixed with the header bits;
outputting the 12 bytes of the interleaver memory from a multiplexor in a certain sequence according to selection signal outputs from the read controller; and
outputting data from the D flip-flop through a wireless transmitter at an accurate timing with clocks by delaying for a certain time period, the D flip-flop being connected to an output terminal of the multiplexor.
According to the above method of this invention, a cell header may be recovered even though continuous errors occurs in 10 or less bits while transmission, since each cell is transmitted by interleaving 40 bits of its header with an interval of 10 bits over the header and payload areas of the cell.
Further, the interleaving is performed in parallel, so that it becomes possible to adopt this interleaving method to a conventional serial processing circuit without any serial/parallel converter. Especially, it becomes possible to reduce operational clocks comparing to the conventional serial processing circuit.